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this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 1 en29lv040a rev. e, issue date: 2011/10/27 purpose eon silicon solution inc. (hereinafter called ?eon?) is going to provide its products? top marking on ics with < cfeon > from january 1st, 2009, and without any change of the part number and the compositions of the ics. eon is still keeping the promise of q uality for all the products with the same as that of eon delivered before. please be advised with the change and appreciate your kindly cooperation and fully support eon?s product family. eon products? new top marking cfeon top marking example: continuity of specifications there is no change to this data sheet as a result of offering the device as an eon product. any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary, where supporte d. future routine revi sions will occur when appropriate, and chan ges will be noted in a revision summary. continuity of ordering part numbers eon continues to support existing part numbers beginning with ?eon? and ?cfeon? top marking. to order these products, during the transition please specify ?eon top marking? or ?cfeon top marking? on your purchasing orders. for more information please contact your local sales office for additional information about eon memory solutions. cfeon part number: xxxx-xxx lot number: xxxxx date code: xxxxx
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 2 en29lv040a rev. e, issue date: 2011/10/27 da0. features ? fully compatible with en29lv040 ? single power supply operation - full voltage range: 2.7-3.6 volt read and write operations for battery-powered applications. - regulated voltage range: 3.0-3.6 volt read and write operations for high performance 3.3 volt microprocessors. ? high performance - access times as fast as 45 ns ? low power consumption (typical values at 5 mhz) - 7 ma typical active read current - 15 ma typical program/erase current - 1 a typical standby current (standard access time to active mode) ? flexible sector architecture: - eight 64 kbyte sectors - supports full chip erase - individual sector erase supported - sector protection and unprotection: hardware locking of sectors to prevent program or erase operations within individual sectors ? high performance program/erase speed - byte/word program time: 8s typical - sector erase time: 500ms typical ? jedec standard program and erase commands ? jedec standard data polling and toggle bits feature ? single sector and chip erase ? embedded erase and program algorithms ? erase suspend / resume modes: read or program another sector during erase suspend mode ? triple-metal double-poly triple-well cmos flash technology ? low vcc write inhibit < 2.5v ? minimum 100k program/erase endurance cycle ? package options - 8mm x 14mm 32-pin tsop (type 1) - 32-pin plcc - 32-pin pdip ? commercial and industrial temperature range general description the en29lv040a is a 4-megabit, electrically erasable, read/write non-volatile flash memory, organized as 524,288 bytes. any byte can be programmed typically in 8s. the en29lv040a features 3.0v voltage read and write operation, with access times as fast as 45ns to eliminate the need for wait states in high-performance microprocessor systems. the en29lv040a has separate output enable ( oe ), chip enable ( ce ), and write enable (we) controls, which eliminate bus contention issues. this device is designed to allow either single sector or full chip erase operation, where each sector can be individually protected against program/erase operations or temporarily unprotected to erase or program. the device can sustain a minimum of 100k program/erase cycles on each sector. en29lv040a 4 megabit (512k x 8-bi t ) uniform sector, cmos 3.0 volt-only flash memory
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 3 en29lv040a rev. e, issue date: 2011/10/27 connection diagrams
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 4 en29lv040a rev. e, issue date: 2011/10/27 table 1. pin description figure 1. logic diagram pin name function a0-a18 addresses dq0-dq7 8 data inputs/outputs we# write enable ce# chip enable oe# output enable vcc supply voltage vss ground table 2. uniform block sector architecture sector address range sector size (kbytes) a18 a17 a16 7 70000h ?7ffffh 64 1 1 1 6 60000h ? 6ffffh 64 1 1 0 5 50000h ? 5ffffh 64 1 0 1 4 40000h ? 4ffffh 64 1 0 0 3 30000h ? 3ffffh 64 0 1 1 2 20000h ? 2ffffh 64 0 1 0 1 10000h ? 1ffffh 64 0 0 1 0 00000h ? 0ffffh 64 0 0 0 en29lv040a dq0 ? dq7 a0 - a18 we# ce# oe#
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 5 en29lv040a rev. e, issue date: 2011/10/27 product selector guide product number en29lv040a regulated voltage range: vcc=3.0-3.6 v -45r -55r speed option full voltage range: vcc=2.7 ? 3.6 v -70 max access time, ns (t acc ) 45 55 70 max ce# access, ns (t ce ) 45 55 70 max oe# access, ns (t oe ) 25 30 30 block diagram we# ce# oe# state control command register erase voltage generator input/output buffers program voltage generator chip enable output enable logic data latch y-decoder x-decoder y-gating cell matrix timer vcc detector a0-a18 vcc vss dq0-dq7 address latch block protect switches stb stb
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 6 en29lv040a rev. e, issue date: 2011/10/27 table 3. operating modes 4m flash user mode table operation ce# oe# we# a0-a18 dq0-dq7 read l l h a in d out write l h l a in d in cmos standby v cc 0.3v x x x high-z output disable l h h x high-z reset x x x x high-z temporary sector unprotect x x x a in d in notes: l=logic low= v il , h=logic high= v ih , v id =11 0.5v, x=don?t care (either l or h, but not floating!), d in =data in, d out =data out, a in =address in table 4. device identifi ction (autoselect codes) 4m flash manufacturer/device id table note: 1. a8 = h is recommended for manufacturing id check. if a manufacturing id is read with a8=l, the chip will output a configuration code 7fh. 2. a9 = vid is for hv a9 autoselect mode only. a9 must be vcc (cmos logic level) for command autoselect mode. description ce# oe# we# a18 to a16 a15 to a10 a9 2 a8 a7 a6 a5 to a2 a1 a0 dq7 to dq0 h 1 1ch manufacturer id: eon l l h x x v id l xl x ll 7fh device id l l h x x v id xxl x lh 4fh 01h (protected) sector protection verification l l h sa x v id xxl x hl 00h (unprotected)
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 7 en29lv040a rev. e, issue date: 2011/10/27 user mode definitions standby mode the en29lv040a has a cmos-compatible standby mode, which reduces the current to < 1a (typical). it is placed in cmos-compatible standby when the ce pin is at v cc 0.3. the device also has a ttl- compatible standby mode, which reduces the maximum v cc current to < 1ma. it is placed in ttl- compatible standby when the ce pin is at v ih . when in standby modes, the outputs are in a high- impedance state independent of the oe input. read mode the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see ?erase suspend/erase resume commands? for more additional information. the system must issue the reset command to re-enable the devic e for reading array data if dq5 goes high, or while in the autoselect mode. see t he ?reset command? additional details. output disable mode when the ce or oe pin is at a logic high level (v ih ), the output from the en29lv040a is disabled. the output pins are placed in a high impedance state. auto select identification mode the autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on dq7?dq0. this mo de is primarily inte nded for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id (11 v) on address pin a9. address pins a8, a6, a1, and a0 must be as shown in autoselect codes table. in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. refer to the corresponding sector address tables. the command definitions table shows the remaining address bits that are don?t-care. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq7?dq0. to access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the command definitions table. this method does not require v id . see ?command definitions? for details on using the autoselect mode. write mode write operations, including programming data and erasing sectors of memory, require the host system to write a command or command sequence to the device. write cycles are initiated by placing the byte or word address on the device?s address inputs while the data to be written is input on dq[7:0]. the host system must drive the ce# and we# pins low and the oe# pin high for a valid write operation to take place. all addresses are latched on the falling edge of we# and ce#, whic hever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. the system is not required to provide further controls or timings. the device automatically provides internally generated program /
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 8 en29lv040a rev. e, issue date: 2011/10/27 erase pulses and verifies the programmed /erased cells? margin. the host system can detect completion of a program or erase operation by re ading the dq[7] (data# polling) and dq[6] (toggle) status bits. the ?command definitions? section of this document provides details on the specific device commands implemented in the en29lv040a. sector protection/unprotection the hardware sector protection feature disables both program and erase operations in any sector. the hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. sector protection/unprotection is intended only for programming equipment. this method requires v id be applied to both oe# and a9 pin and non-standard microprocessor timings are used. this method is described in a separate document called en29lv040a supplement, which can be obtained by contacting a representative of eon silicon solution, inc. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30ns. the automatic sleep mode is independent of the ce#, we# and oe# control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output is latched and always available to the system. icc 4 in the dc characteristics table represents the automatic sleep more current specification. hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes as seen in the command definitions table. additionally, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by false system level signals during vcc power up and power down transitions, or from system noise. low v cc write inhibit when vcc is less than v lko , the device does not accept any write cycles. this protects data during vcc power up and power down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until vcc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when vcc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe , ce or we do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe = vil, ce = vih, or we = vih. to initiate a write cycle, ce and we must be a logical zero while oe is a logical one. if ce , we , and oe are all logical zero (not reco mmended usage), it will be considered a read. power-up write inhibit during power-up, the device automatically resets to read mode and locks out write cycles. even with ce = v il , we = v il and oe = v ih , the device will not accept co mmands on the rising edge of we .
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 9 en29lv040a rev. e, issue date: 2011/10/27 command definitions the operations of the en29lv040a are selected by one or more commands written into the command register to perform read/reset memory, read id, read sector protection, program, sector erase, chip erase, erase suspend and erase resume. commands are made up of data sequences written at specific addresses via the command register. the sequences for the specified operation are defined in the command definitions table (table 5). incorrect addresses, incorrect data values or improper se quences will reset the de vice to read mode. table 5. en29lv040a command definitions bus cycles 1 st cycle 2 nd cycle 3 rd cycle 4 th cycle 5 th cycle 6 th cycle command sequence cycles add data add data add data add data add data add data read 1 ra rd reset 1 xxx f0 000 7f manufacturer id 4 555 aa 2aa 55 555 90 100 1c device id 4 555 aa 2aa 55 555 90 x01 4f autoselect sector protect verify 4 555 aa 2aa 55 555 90 (sa) x02 00/ 01 program 4 555 aa 2aa 55 555 a0 pa pd chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend 1 xxx b0 erase resume 1 xxx 30 address and data values indicated in hex ra = read address: address of the memory location to be read. this is a read cycle. rd = read data: data read from location ra during read operation. this is a read cycle. pa = program address: address of the memory location to be programmed. x = don?t-care pd = program data: data to be programmed at location pa sa = sector address: address of the sector to be erased or verified. address bits a18-a16 uniquely select any sector. reading array data the device is automatically set to reading array data after power up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. following an erase suspend command, erase suspend mode is entered. the system can read array data using the standard read timings, with the only difference in that if it reads at an address within erase suspended sectors, the device outp uts status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. the reset command must be issued to re-enable the device for reading array data if dq5 goes high, or while in the autoselect mode. see ne xt section for details on reset.
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 10 en29lv040a rev. e, issue date: 2011/10/27 autoselect command sequence the autoselect command sequence allows the host syst em to access the manufact urer and devices codes, and determine whether or not a sector is protected. the command definitions table shows the address and data requirements. this is an altern ative to the method that requires v id on address bit a9 and is intended for prom programmers. two unlock cycles followed by the autoselect comm and initiate the autosel ect command sequence. autoselect mode is then entered and the system may read at addresses shown in table 4 any number of times, without needing another command sequence. the system must write the reset comma nd to exit the autoselect mode and return to re ading array data. programming command programming the en29lv040a is performed by using a four bus-cycle operation (two unlock write cycles followed by the program setup command and program data write cycle). when the program command is executed, no additional cpu controls or timings are necessary. an internal timer terminates the program operation automatically. address is latched on the falling edge of ce or we , whichever is last; data is latched on the rising edge of ce or we , whichever is first. programming status may be checked by sampling data on dq7 ( dat a polling) or on dq6 (toggle bit). when the program operation is successfully completed, the device returns to read mode and the user can read the data programmed to the device at that address. note that data can not be programmed from a 0 to a 1. only an erase operation can change a data from 0 to 1. when programming time limit is exceeded, dq5 will produce a logi cal ?1? and a reset command can re turn the device to read mode. chip erase command chip erase is a six-bus-cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embe dded erase algorithm automatically pr eprograms and verifies the entire memory for an all zero data pattern prior to electric al erase. the system is not required to provide any controls or timings during these operations. the co mmand definitions table shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the embedded chip erase algorithm are ignored. the system can determine the status of the erase operation by using dq7, dq6, or dq2. see ?write operation status? for information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. flowchart 4 illustrates the algorithm fo r the erase operation. see the erase/ program operations tables in ?ac characteristics? for parameters, a nd to the chip/sector erase operati on timings for timing waveforms. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two un- lock cycles, followed by a set-up co mmand. two additional unlock writ e cycles are then followed by the address of the sector to be erased, and the sector erase command. the command definitions table shows the address and data requirements for the sector erase command sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latc hed. the system can determine th e status of the erase operat ion by using dq7, dq6, or
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 11 en29lv040a rev. e, issue date: 2011/10/27 dq2. refer to ?write oper ation status? for information on these status bits. flowchart 4 illustrates the algorithm for the erase operation. refer to the erase/pr ogram operations tables in the ?ac characteristics? section for parameters, and to the sector erase operations timing diagram for timing waveforms. erase suspend / resume command the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for er asure. this command is valid only during the sector erase operation. the erase suspend command is ignor ed if written during the chip erase operation or embedded program algorithm. addresses are don?t- cares when writing the erase suspend command. when the erase suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. after the erase operation ha s been suspended, the system can read ar ray data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) normal read and write timings and command defini tions apply. reading at any address within erase-suspended sectors produces status data on dq7?dq0. the system can use dq7, or dq6 and dq2 toge ther, to determine if a sector is actively erasing or is er ase-suspended. see ?write operation stat us? for information on these status bits. after an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operati on. see ?write operation status? for more information. the autoselect command is not supported during erase suspend mode. the system must write the erase resu me command (address bits are don?t- care) to exit th e erase suspend mode and continue the sector erase operation. furthe r writes of the resume command are ignored. another erase suspend command can be written after the device has resumed erasing. write operation status dq7: dat a polling the en29lv040a provides data polling on dq7 to indicate to th e host system the status of the embedded operations. the data polling feature is active during the embedded pr ogramming, sector erase, chip erase, erase suspend. (see table 6) when the embedded programming is in progress, an attempt to read the device will produce the complement of the data last written to dq7. upon the completion of the embedded programming, an attempt to read the device will produce the true data last written to dq 7. for the embedded programming, data polling is valid after the rising edge of the fourth we or ce pulse in the four- cycle sequence. when the embedded erase is in pr ogress, an attempt to read the de vice will produce a ?0? at the dq7 output. upon the completion of the embedded erase, the de vice will produce the ?1 ? at the dq7 output during the read. for chip erase, the data polling is valid after the rising edge of the sixth we or ce pulse in the six-cycle sequence. for sector erase, data polling is valid after the last rising edge of the sector erase we or ce pulse. data polling must be performed at an y address within a sector that is being programmed or erased and not a protected sector. otherwise, data polling may give an inaccurate result if the address used is in a protected sector. just prior to the completion of the embedded operations, dq7 may change asynchronously when the output enable ( oe ) is low. this means that the device is driving status information on dq7 at one
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 12 en29lv040a rev. e, issue date: 2011/10/27 instant of time and valid data at the next instant of time. depending on when the system samples the dq7 output, it may read the status of valid data. even if the device has completed the embedded operations and dq7 has a valid data, the data output on dq0-dq6 may be still invalid. the valid data on dq0-dq7 will be read on the subsequent read attempts. the flowchart for data polling (dq7) is shown on flowchart 5. the data polling (dq7) timing diagram is shown in figure 8. dq6: toggle bit i the en29lv040a provides a ?toggle bit? on dq6 to indicate to the host system the status of the embedded programming and erase operations. (see table 6) during an embedded program or erase operation, successive attempts to read data from the device at any address (by toggling oe or ce ) will result in dq6 to ggling between ?zero? an d ?one?. once the embedded program or erase operatio n is complete, dq6 will stop togg ling and valid data will be read on the next successive attempts. during byte programming, the toggle bit is valid after the rising edge of the fourth we pulse in the four-cycle sequence. for chip erase, the toggle bit is valid after the rising edge of the sixth-cycle sequence. for sector erase, the toggle bit is valid after the last rising edge of the sector erase we pulse. in byte programming, if the sector being writte n to is protected, dq6 will toggles for about 2 s, then stop toggling without the data in the sector having changed. in sector erase or chip erase, if all selected blocks are protected, dq6 will toggle for about 100 s. the chip will then return to the read mode without changing data in all protected blocks. toggling either ce or oe will cause dq6 to toggle. the flowchart for the toggle bit (dq6) is shown in flowchart 6. the toggle bit timing diagram is shown in figure 9 . dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1.? this is a failure condition that indicates the program or erase cycle was not successfully completed. since it is possible that dq5 can become a 1 when the device has successfully completed its operation and has returned to read mode, the user must check again to see if the dq6 is toggling after detecting a ?1? on dq5. the dq5 failure condition may appear if the system tries to program a ?1? to a location that is previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the operation has exceeded the timing limits, dq5 produces a ?1.? under both these conditions, the system must issue the reset command to return the device to reading array data. dq3: sector erase timer after writing a sector erase command sequence, the output on dq3 can be used to determine whether or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) when sector erase starts, dq3 switches fr om ?0? to ?1.? this device does not support multiple sector erase command sequences so it is not very meaningful since it immediately shows as a ?1? after the first 30h command. future devices may support this feature.
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 13 en29lv040a rev. e, issue date: 2011/10/27 dq2: erase toggle bit ii the ?toggle bit? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to table 5 to compare outputs for dq2 and dq6. flowchart 6 shows the toggle bit algorithm, and the section ?dq2: toggle bit? explains the algorithm. see also the ?dq6: toggle bit i? subsection. refer to the toggle bit timings figure for the toggle bit timing diagram. the dq2 vs. dq6 figure shows t he differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to flowchart 6 for th e following discussion. whenever the system initially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or eras e operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that th e toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the se ction on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operati on. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset comm and to return to reading array data. the remaining scenario is that the syst em initially determines that the to ggle bit is toggli ng and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of flowchart 6).
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 14 en29lv040a rev. e, issue date: 2011/10/27 write operation status operation dq7 dq6 dq5 dq3 dq2 embedded program algorithm dq7# toggle 0 n/a no toggle standard mode embedded erase algorithm 0 toggle 0 1 toggle reading within erase suspended sector 1 no toggle 0 n/a toggle reading within non-erase suspended sector data data data data data erase suspend mode erase-suspend program dq7# toggle 0 n/a n/a table 6. status register bits dq name logic level definition ?1? erase complete or erase sector in erase suspend ?0? erase on-going dq7 program complete or data of non-erase sector during erase suspend 7 data polling dq7 program on-going ?-1-0-1-0-1-0-1-? erase or program on-going dq6 read during erase suspend 6 toggle bit ?-1-1-1-1-1-1-1-? erase complete ?1? program or erase error 5 time out bit ?0? program or erase on-going ?1? erase operation start 3 erase time out bit ?0? erase timeout period on-going ?-1-0-1-0-1-0-1-? chip erase, erase or erase suspend on currently addressed sector. (when dq5=1, erase error due to currently addressed sector. program during erase suspend on-going at current address 2 toggle bit dq2 erase suspend read on non erase suspend sector notes: dq7 data polling: indicates the p/e c status check during program or erase, and on completion before checking bits dq5 for program or erase success. dq6 toggle bit: remains at constant level when p/e operations are complete or erase suspend is acknowledged. successive reads output complementary data on dq6 while programming or erase operation are on-going. dq5 time out bit: set to ?1? if failure in programming or erase dq3 sector erase command timeout bit: operation has started. only possible command is erase suspend (es). dq2 toggle bit: indicates the erase status and allows identification of the erased sector.
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 15 en29lv040a rev. e, issue date: 2011/10/27 embedded algorithms flowchart 1. embedded program star t write program command sequen ce (shown below) data poll device last address? prog ra mming done increment address no yes verify data? no yes flowchart 2. embedded program command sequence 2aah/55h 555h/ a ah 555h/a0h program address / program data
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 16 en29lv040a rev. e, issue date: 2011/10/27 flowchart 3. embedded erase flowchart 4. embedded erase command sequence chip erase sector erase 2aah/55h 555h/aah 555h/80h 2aah/55h 555h/aah 555h/10h 555h/aah 2aah/55h 555h/80h 555h/aah 2aah/55h sector address/30h start write erase command sequence data poll from system or toggle bit successfully completed erase done data =ffh? yes no
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 17 en29lv040a rev. e, issue date: 2011/10/27 flowchart 5. dat a polling algorithm notes: (1) this second read is necessary in case the first read was done at the exact instant when the status data was in transition. flowchart 6. toggle bit algorithm notes: (1) this second set of reads is necessary in case the first set of reads was done at the exact instant when the status data was in transition. no yes dq6 = toggle? dq5 = 1? dq6 = toggle? no no yes yes read data twice start read data twice (2) fail pass no no dq7 = data? dq5 = 1? dq7 = data? yes yes no yes read data start read data (1) fail pass
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 18 en29lv040a rev. e, issue date: 2011/10/27 table 7. dc characteristics (t a = 0c to 70c or - 40c to 85c; v cc = 2.7-3.6v) symbol parameter test conditions min typ max unit i li input leakage current 0v v in vcc 1 a i lo output leakage current 0v v out vcc 1 a i cc1 supply current (read - cmos) ce# = v il ; oe# = v ih ; f = 5mhz 7 12 ma i cc2 supply current (standby - cmos) ce# = vcc 0.3v 1 5.0 a i cc3 supply current (program or erase) byte program, sector or chip erase in progress 15 30 ma i cc4 automatic sleep mode v ih = vcc 0.3 v v il = vss 0.3 v 1 5.0 a v il input low voltage -0.5 0.8 v v ih input high voltage 0.7 x vcc vcc + 0.3 v v ol output low voltage i ol = 4.0 ma 0.45 v v oh output high voltage cmos i oh = -100 a, vcc - 0.4v v v id a9 voltage (electronic signature) 10.5 11.5 v i id a9 current (electronic signature) a9 = v id 100 a v lko supply voltage (erase and program lock-out) 2.3 2.5 v
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 19 en29lv040a rev. e, issue date: 2011/10/27 test conditions test specifications test conditions -4 5r -55r -70 unit output load capacitance, c l 30 30 30 pf input rise and fall times 5 5 5 ns input pulse levels 0.0-3.0 0.0-3.0 0.0-3.0 v input timing measurement reference levels 1.5 1.5 1.5 v output timing measurement reference levels 1.5 1.5 1.5 v device under test c l
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 20 en29lv040a rev. e, issue date: 2011/10/27 table 8. ac characteristics read-only operations characteristics parameter symbols speed options jedec standard description test setup -45r -55r -70 unit t avav t rc read cycle time min 45 55 70 ns t avqv t acc address to output delay ce = v il oe = v il max 45 55 70 ns t elqv t ce chip enable to output delay oe = v il max 45 55 70 ns t glqv t oe output enable to output delay max 25 30 30 ns t ehqz t df chip enable to output high z max 10 15 20 ns t ghqz t df output enable to output high z max 10 15 20 ns t axqx t oh output hold time from addresses, ce or oe , whichever occurs first min 0 0 0 ns notes: for -45r,-55r,70 vcc = 3.0v 5% output load : 30pf input rise and fall times: 5ns input rise levels: 0.0 v to vcc timing measurement reference level, input and output: 1.5 v figure 5. ac waveforms for read operations addresses ce# oe# we# outputs t b acc 0v high z output valid t b ce b t b oh t b df t b oeh b high z t b oe b t b rc b addresses stable
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 21 en29lv040a rev. e, issue date: 2011/10/27 table 9. ac characteristics write (erase/program) operations parameter symbols speed options jedec standard description -45r -55r -70 unit t avav t wc write cycle time min 45 55 70 ns t avwl t as address setup time min 0 0 0 ns t wlax t ah address hold time min 35 45 45 ns t dvwh t ds data setup time min 20 25 30 ns t whdx t dh data hold time min 0 0 0 ns t oes output enable setup time min 0 0 0 ns read min 0 0 0 ns t oeh output enable hold time toggle and data polling min 10 10 10 ns t ghwl t ghwl read recovery time before write ( oe high to we low) min 0 0 0 ns t elwl t cs ce setuptime min 0 0 0 ns t wheh t ch ce hold time min 0 0 0 ns t wlwh t wp write pulse width min 25 30 35 ns t whdl t wph write pulse width high min 20 20 20 ns typ 8 8 8 s t whwh1 t whwh1 programming operation max 300 300 300 s t whwh2 t whwh2 sector erase operation typ 0.5 0.5 0.5 s t vcs vcc setup time min 50 50 50 s t vidr rise time to v id min 500 500 500 ns
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 22 en29lv040a rev. e, issue date: 2011/10/27 table 10. ac characteristics write (erase/program) operations alternate ce controlled writes parameter symbols speed options jedec standard description -45r -55r -70 unit t avav t wc write cycle time min 45 55 70 ns t avel t as address setup time min 0 0 0 ns t elax t ah address hold time min 35 45 45 ns t dveh t ds data setup time min 20 25 30 ns t ehdx t dh data hold time min 0 0 0 ns t oes output enable setup time min 0 0 0 ns read min 0 0 0 ns t oeh output enable hold time toggle and data polling min 10 10 10 ns t ghel t ghel read recovery time before write ( oe high to ce low) min 0 0 0 ns t wlel t ws we setuptime min 0 0 0 ns t ehwh t wh we hold time min 0 0 0 ns t eleh t cp write pulse width min 25 30 35 ns t ehel t cph write pulse width high min 20 20 20 ns typ 8 8 8 s t whwh1 t whwh1 programming operation max 300 300 300 s t whwh2 t whwh2 sector erase operation typ 0.5 0.5 0.5 s t vcs vcc setup time min 50 50 50 s t vidr rise time to v id min 500 500 500 ns
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 23 en29lv040a rev. e, issue date: 2011/10/27 table 11. erase and programming performance limits parameter typ max unit comments sector erase time 0.5 10 sec chip erase time 4 80 sec excludes 00h programming prior to erasure byte programming time 8 300 s chip programming time 4.2 12.6 sec excludes system level overhead erase/program endurance 100k cycles minimum 100k cycles table 12. data retention parameter description test conditions min unit 150c 10 years data retention time 125c 20 years table 13. tsop pin capacitance @ 25c, 1.0mhz parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 7.5 9 pf table 14. 32-pin plcc pin capacitance @ 25c, 1.0mhz parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 4 6 pf c out output capacitance v out = 0 8 12 pf c in2 control pin capacitance v in = 0 8 12 pf
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 24 en29lv040a rev. e, issue date: 2011/10/27 ac characteristics figure 6. ac waveforms for chip/sector erase operations timings notes: 1. sa=sector address (for sector erase) , va=valid address for reading status, d out =true data at read address. 2. v cc shown only to illustrate t vcs measurement references. it cannot o ccur as shown during a valid command sequence. 10 for chip erase t dh t d s 0x55 0x30 status d ou t t whwh 2 v cc a ddresses ce# oe# we# data t c h t g hw l t c s t wph t wp t v cs erase command sequence (last 2 cycles) read status data (last two cycles) t ah t w c 0x2aa s a v a v a t a s 0x555 for chip erase
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 25 en29lv040a rev. e, issue date: 2011/10/27 figure 7. program operation timings notes: 1. pa=program address, pd=program data, d out is the true data at the program address. 2. v cc shown in order to illustrate t vcs measurement references. it cannot occur as shown during a valid command sequence. t vcs t whwh1 t ds t dh d out status pd oxa0 t ah t as t wc 0x555 pa pa pa program command sequence (last 2 cycles) program command sequence (last 2 cycles) t ghwl data v cc we# addresses ce# oe# t ch t wph t cs t wp
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 26 en29lv040a rev. e, issue date: 2011/10/27 figure 8. ac waveforms for /data polling during embedded algorithm operations notes: 1. va=valid address for reading data# polling status data 2. this diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cy cle. figure 9. ac waveforms for toggle bit during embedded algorithm operations t oeh t df t o e t c e t c h t a cc t r c v a v a va t o h valid data true com p lement comple -ment status data status data true valid data ce# addresses oe# we# dq[7] dq[6:0] t c e t o e t c h valid data valid status valid status valid status (first read) (second read) (stops toggling) a ddresses ce# oe# we# dq6, dq2 t r c t a cc v a v a v a v a t o eh t df t o h
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 27 en29lv040a rev. e, issue date: 2011/10/27 figure 10. alternate ce# controlled write operation timings notes: pa = address of the memory lo cation to be programmed. pd = data to be programmed at byte address. va = valid address for reading program or erase status d out = array data read at va figure 11. dq2 vs. dq6 we# dq6 dq2 enter embedded erase erase suspend enter erase suspend program erase resume erase enter suspend read enter suspend program erase erase complete erase suspend read t wh t ghel t cp pd for program 0x30 for sector erase 0x10 for chip erase 0xa0 for program 0x55 for erase d out status t ds t dh t cph t ws t whwh1 / t whwh2 addresses we# oe# ce# data t ah t as t wc va pa for program sa for sector erase 0x555 for chip erase 0x555 for program 0x2aa for erase
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 28 en29lv040a rev. e, issue date: 2011/10/27 absolute maximum ratings parameter value unit storage temperature -65 to +150 c plastic packages -65 to +125 c ambient temperature with power applied -55 to +125 c output short circuit current 1 200 ma a9 and oe# 2 -0.5 to +11.5 v all other pins 3 -0.5 to vcc+0.5 v voltage with respect to ground vcc -0.5 to +4.0 v notes: 1. no more than one output shorted at a time. duration of the short circuit should not be greater than one second. 2. minimum dc input voltage on a9 and oe# pins is ?0.5v. during voltage transitions, a9 and oe# pins may undershoot v ss to ? 1.0v for periods of up to 50ns and to ?2.0v for periods of up to 20ns. see figure below. maximum dc input voltage on a9 and oe# is 11.5v which may overshoot to 12.5v for periods up to 20ns. 3. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, inputs may undershoot v ss to ?1.0v for periods of up to 50ns and to ?2.0 v for periods of up to 20ns. see figure below. maximum dc voltage on output and i/o pins is v cc + 0.5 v. during voltage transitions, outputs may overshoot to v cc + 1.5 v for periods up to 20ns. see figure below. 4. stresses above the values so mentioned above may cause permanent damage to the device. these values are for a stress rating only and do not imply that the device should be operated at conditions up to or above these values. exposure of the device to the maximum rating values for extended periods of time may adversely affect the device reliability. recommended operating ranges 1 parameter value unit ambient operating temperature commercial devices industrial devices 0 to 70 -40 to 85 c regulated voltage range: 3.0-3.6 operating supply voltage vcc standard voltage range: 2.7 to 3.6 v 1. recommended operating ranges define those limits between which the functionality of the device is guaranteed. vcc +1.5v maximum negative overshoot maximum positive overshoot waveform waveform
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 29 en29lv040a rev. e, issue date: 2011/10/27 physical dimensions pl 032 32-pin plastic leaded chip carrier
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 30 en29lv040a rev. e, issue date: 2011/10/27 physical dimensions (continued) pd 032 32-pin plastic dip
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 31 en29lv040a rev. e, issue date: 2011/10/27 physical dimensions (continued) 32l tsop-1 8mm x 14mm
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 32 en29lv040a rev. e, issue date: 2011/10/27 ordering information en29lv040a 70 s c p packaging content p = rohs compliant temperature range c = commercial (0 c to +70 c) i = industrial (-40 c to +85 c) package p = 32 plastic dip j = 32-pin plastic plcc s = 32-pin 8mm x 14mm tsop-1 speed 45r = 45ns regulated range 3.0v~3.6v 55r = 55ns regulated range 3.0v~3.6v 70 = 70ns base part number en = eon silicon solution inc. 29lv = flash, 3v read program erase 040 = 4 megabit (512k x 8) uniform sector a = version a
this data sheet may be revised by subsequent versions ? 2003 eon silicon solution, inc., www.eon ssi.com or modifications due to changes in technical specifications. 33 en29lv040a rev. e, issue date: 2011/10/27 revisions list revision no description date a initial draft 2005/08/15 b 1. add 32 pin pdip for package options in page 1 2. add 32 pin pdip diagram in page 2 3. add 32-pin pdip in physical dimensions in page 32 4. add 32 pin pdip package option ?p? to ordering information in page 35 2007/01/05 c 1. add eon products? new top marking ?cfeon? information in page 1. 2. remove package 8mm x 20mm 32-pin tsop 2009/01/09 d 1. add the chip will output a configurat ion code 7fh, if a manufacturing id is read with a8 = l (000h). 2. modify test conditions illustration on page 19. 3. modify storage temperature from "-65 to + 125" to "-65 to +150" on page 28. 4. remove the latch up characteristics table. 2011/05/03 e correct the typo of v ih (max.) = vcc + 0.3v on page 18. 2011/10/27

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